Nowadays, communication networks are more and more complicated, and new services are emerging constantly, which imposes higher requirements on the capability of controlling network traffic and network security. As the core of a network system, the communication processor encounters great challenges. To meet the high-bandwidth requirement, a Multi-Core Processor emerges.
The Multi-Core Processor is challenged by many technical difficulties in the communication process. One of the difficulties is to enforce order of packets, Multiple cores process various packets parallelly. For the packets in a same stream, each core needs to distribute the packets in First In First Out (FIFO) order. Generally, the delays of processing packets by the cores are different. Consequently, the processing of a packet that arrives earlier may be completed later, and the processing of a packet that arrives later may be completed earlier, which will disorder the packets and affect the service streams.
One processing mode applied in the communication process of a Multi-Core Processor is the pipeline mode. In the pipeline mode, one packet is processed by multiple cores jointly, each core is responsible for a specific stage of the packet processing, and finally, a processing result is output. Because packets in one stream are processed in multiple stages before the processing result is output, the original order of the packets needs to be kept when the packet processing switches from the egress of a processing stage to the ingress of the next processing stage.
In the pipeline mode in the prior art, the order of packets is enforced in the following way:
As shown in FIG. 1, a Critical Section Round Robin (CSRR) mode is applied in the prior art. The cores perform the reading operation, processing operation and writing operation for a packet sequentially. If core 0 has not finished the writing operation but core 1 has finished the processing operation, core 1 has to wait; and the subsequent cores have to wait so that the output packets can be kept in order.
In the prior art, a core may spend much time in waiting for completion of the operation of the previous core, which deteriorates the processing efficiency of cores.